I have been an application-specific IC (ASIC) designer for nearly three decades. During that time, I have moved through the full academic track, from graduate student to full professor; later, I switched to industry after failing in business. When I switched to the private sector in 2019, I began to focus on the most important aspect of the electronic sector: silicon intellectual property.
About 80 percent of the physical space in today’s most advanced chips is occupied by blocks that are not made for specific products or even designed by the consumer-facing companies that make them. Instead, chipmakers are drawing heavily on silicon IP developed by companies like Arm, Cadence, Rambus, Synopsys, and the company I work for, Silicon Creations.
Throughout my career, I have designed chips for very different purposes, including powering a research program in my academic lab and expanding my company’s IP portfolio. When I joined Silicon Creations, I had no idea how the industry looked at IC design differently and encountered a steep learning curve. At first, it seemed that much of my two decades of research and academic training did not translate directly into the role. I had to learn new skills and have a new way of thinking.
Today, the demand for ASICs is growing rapidly, driven by the need for specialized chips in the automotive sector, AI applications, and more. According to one market estimate, the ASIC market is expected to grow from US $23.4 billion to $38.8 billion by 2033, and the overall semiconductor industry is expected to reach $1 trillion by 2030. The industry needs more chip designers—but if you come from an academic background like I do, there are a few things you’ll need to know.
Different goals lead to different strategies
The difference between industry and academia starts with the difference in purpose. In academics, my main goal was to generate new knowledge: to propose a new circuit method, to validate an unusual design, or to test the limits of performance in a specific domain. A successful chip is one that makes sense. In industry, it’s not enough to prove that something can work. The goal is to ensure that it works reliably, repeatedly, and at scale. Success is not measured by innovation but by whether the silicon meets specifications, yields as expected in production, and supports a competitive product delivered on time.
This leads to a big difference in risk tolerance. Educational projects often deliberately move into unproven territory, where even modest success may yield important insights. In the industry, however, we reduce risk systematically. Failure costs make early silicon success a critical requirement—especially in advanced technology areas, where mask lithography used to transfer circuit designs onto silicon wafers alone can cost tens of millions of dollars. As a result, the industry’s design flow is built on eliminating uncertainty through conservative margins, extensive validation, and careful reuse of proven solutions.
“Academia explores the design space, asking what is possible, while industry uses it, deciding what works at scale.”
This paradigm has been around since the 1970s, when application-specific chip design was invented. However, the gap between academia and industry has widened since the mid-2010s, when FinFET technology, a 3D structure using vertical silicon “fins”, was widely adopted in industry. System designs are also becoming increasingly modular with the advent of chiplets. This dramatically changed the economics and complexity of ASIC development, with design costs increasing by almost an order of magnitude. Initiatives like Taiwan Semiconductor Manufacturing Co.’s University FinFET Program and new government-funded chip-design hubs now allow some well-resourced universities to design more advanced architectures, but the technology is still out of reach for most academics.
What the separation of industry and academia means in practice
Consider an ASIC development startup. Its engineering team may have deep expertise in a particular algorithm, sensor interface, or system architecture, factors that define its competitive advantage. But you are less likely to have world-class experience in every support function. Developing each of these blocks internally will require significant time, money, and specialized talent. Doing so may delay market penetration beyond launch capacity.
Even large semiconductor companies face similar challenges. Advanced node development requires a lot of focus. Assigning a team to redesign a common interface block already made elsewhere may be difficult to justify when the separation is at the system level, such as the inference chip’s ability to accelerate neural network computations. The time it takes to move a new chip from design to market and risk mitigation, not self-sufficiency, govern many decisions about in-house development versus outsourcing.
The economics of advanced IC manufacturing reinforce this fact. When the cost of developing a leading-edge chip reaches hundreds of millions of dollars, risk mitigation becomes a design imperative.
In this context, silicon IP emerged as a viable solution. Similar to how software developers rely on existing libraries rather than writing entire functions from scratch, ASIC designers license pre-designed, pre-certified silicon blocks—such as processor cores, memory interfaces, and security engines—from specialized IP vendors. These blocks can then be combined into larger, more complex systems.
Design scope, validation, and time horizons
With the use of silicon IP, the industry is able to expand the scope of its designs. Academic efforts tend to focus on block-level innovation: a new design for an analog-to-digital converter or a very low-noise amplifier, for example. These designs often eliminate many of the complexities of bringing a chip to market, such as packaging constraints, long-term reliability, and manufacturing yield.
In industry, the focus is shifting to system-level integration. Modern systems on chips, or SoCs, consist of dozens or even hundreds of functional blocks. Managing signal integrity, timing, firmware compatibility, and system-level authentication becomes as critical as the design of any individual block.
The philosophy of authentication also varies greatly. In academia, the goal of validation is to show that a concept works under typical conditions, which may not always reflect how it will perform in real applications. Even if only a small fraction of the chips built from a multiproject wafer work correctly, the design can be considered a success if it validates the basic concept.
For example, in my academic lab, we used to get 40 chips from TSMC’s prototyping service and start testing them in batches of five. If the first five or 10 chips appear to work, then we have collected more than enough data to publish. If some of them failed, we didn’t have to mention this when we published the results.
In industry, validation is finite, critical, and often dominates the development schedule. Failures are measured in parts per million, and even rare anomalies are carefully analyzed and documented to determine root causes and prevent recurrence. When I first started at Silicon Creations, I was amazed at the level of detail and the meticulous designs they faced.
Differences in time horizons and economic constraints reinforce each of these contrasts. Academic projects operate at flexible times associated with research and funding cycles. If I missed the deadline, I had to wait for the next round. Industrial projects are driven by fixed product schedules and market windows, often targeting high-cost nodes to achieve competitive performance, capacity, and spatial efficiency. Missing a deadline can devalue the entire design and can have major financial consequences throughout the supply chain.
In short, academics explore the design environment, asking what is possible, while industry uses, determines what works at scale. Both are important, but operate under very different definitions of success. As the complexity of ASICs continues to increase, understanding both concepts will be important to the next generation of engineers navigating the changing semiconductor landscape.
This article appears in the June 2026 issue.
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